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1999 data sheet description the m pd178023, 178024 are 8-bit single-chip cmos microcontrollers containing hardware for digital tuning systems. these microcontrollers employ a 78k/0 series architecture cpu and allow easy access to internal memories at high speed and easy control of peripheral hardware units. the high-speed 78k/0 series instructions are ideal for system control. as peripheral hardware, a prescaler, pll frequency synthesizer, and frequency counter for digital tuning systems are provided, as well as many i/o ports, timers, a/d converter, serial interface, and a power-on clear circuit. in addition, three serial interfaces, i 2 c bus (iic0), three-wire (sio3), and uart are provided. moreover, a flash memory model, the m pd178f124, that operates in the same supply voltage range as the mask rom models, and various development tools are also under development. for the detailed functional description, refer to the following users manuals: m pd178024, 178124 subseries users manual : u13915e 78k/0 series users manual - instruction : u12326e features high-capacity rom and ram item program memory (rom) data memory part number internal high-speed ram m pd178023 24k bytes 1024 bytes m pd178024 32k bytes mos integrated circuit m pd178023,178024 document no. u14126ej1v0ds00 (1st edition) date published september 1999 n cp(k) printed in japan 8-bit single-chip microcontroller instruction cycle: 0.45/0.89/1.78/3.56/7.11 m s (with crystal resonator of f x = 4.5 mhz) many internal hardware units general-purpose i/o ports, a/d converter, serial interface (i 2 c bus and uart mode), timers, frequency counter, power-on clear circuit hardware for pll frequency synthesizer dual modulus prescaler, programmable divider, phase comparator, charge pump vectored interrupt sources: 17 supply voltage :v dd = 4.5 to 5.5 v (during pll and cpu operations) :v dd = 3.5 to 5.5 v (during cpu operation) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd178023, 178024 data sheet u14126ej1v0ds00 application field car stereos ordering information part number package m pd178023gf- -3b9 80-pin plastic qfp (14 20 mm, 0.8-mm pitch) m pd178023gc- -8bt 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178024gf- -3b9 80-pin plastic qfp (14 20 mm, 0.8-mm pitch) m pd178024gc- -8bt 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) remark indicates rom code suffix, which is e when the i 2 c bus is used.
3 m pd178023, 178024 data sheet u14126ej1v0ds00 development of 8-bit dts series pd178f048 pd178f098 pd178f134 pd178f124 pd178p018a m models under mass production models under development flash memory model or prom model mask rom model m m m m 64/80 pins 100 pins 80 pins 80 pins 80 pins 64/80 pins 100 pins 80 pins 80 pins 80 pins 80 pins pd178048 subseries pd178078 subseries pd178034 subseries pd178024 subseries pd178003 subseries pd178018a subseries pd178098 subseries internal osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel internal osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel m m m m m m m 100 pins internal iebus tm controller and uart internal lcd and uart internal uart internal iebus controller internal uart internal lcd and uart internal uart limits functions of pd178018a subseries m
4 m pd178023, 178024 data sheet u14126ej1v0ds00 functional outline (1/2) item m pd178023 m pd178024 internal rom 24 kbytes 32 kbytes memory (mask rom) (mask rom) high-speed ram 1024 bytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.45 m s/0.89 m s/1.78 m s/3.56 m s/7.11 m s (with crystal resonator of f x = 4.5 mhz) instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. i/o port total : 62 pins ? cmos i/o : 53 pins ? cmos input : 6 pins ? n-ch open-drain output : 3 pins a/d converter 8-bit resolution 6 channels (v dd = 4.5 to 5.5 v) serial interface ? i 2 c bus mode note : 1 channel ? 3-wire mode : 1 channel ? uart mode : 1 channel timer ? basic timer (timer carry ff (10 hz)) : 1 channel ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel buzzer output 1 channel (1 khz, 1.5 khz, 3 khz, 4 khz) vectored maskable internal : 11 interrupt external: 5 source non-maskable internal: 1 software internal: 1 pll division mode 2 types frequency ? direct division mode (vcol pin) synthesizer ? pulse swallow mode (vcol and vcoh pins) reference frequency seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 khz) charge pump error out output: 2 pins phase comparator unlock detectable in software note when the i 2 c bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult nec when ordering a mask.
5 m pd178023, 178024 data sheet u14126ej1v0ds00 (2/2) item m pd178023 m pd178024 frequency counter frequency measurement ? amifc pin: for 450-khz counting ? fmifc pin: for 450-khz/10.7-mhz counting reset ? reset by reset pin ? internal reset by watchdog timer ? reset by power-on clear circuit ? detection of less than 4.5 v note (reset does not occur, however.) ? detection of less than 3.5 v note (during cpu operation) ? detection of less than 2.3 v note (in stop mode) supply voltage ? v dd = 4.5 to 5.5 v (during cpu, pll operation) ?v dd = 3.5 to 5.5 v (during cpu operation) package ? 80-pin plastic qfp (14 20 mm, 0.8-mm pitch) ? 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) note these voltages are the maximum values. in practice, the chip may be reset at voltages lower than these.
6 m pd178023, 178024 data sheet u14126ej1v0ds00 pin configuration (top view) ? 80-pin plastic qfp (14 20 mm, 0.8 pitch) m pd178023gf- -3b9, 178024gf- -3b9 cautions 1. directly connect the ic (internally connected) to gnd. 2. keep the voltage at v dd port and v dd pll at the same voltage as v dd . 3. keep the voltage at gndport and gndpll at the same voltage as gnd. 4. connect each of the regosc and regcpu pins to gnd via 0.1- m f capacitor. p121 p120 p37 p36/beep0 p35 p34/ti51 p33/ti50 p32 p31 p30 p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 p55 p54 p53 p52 v dd reset p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p70/si3 p71/so3 p72/sck3 p73 p74/rxd0 p75/txd0 p76/sda0 p77/scl0 p130/to50 p131/to51 p132 p40 p41 p42 gndport v dd port 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p43 p44 p45 p46 p47 amifc fmifc v dd pll gndpll vcoh vcol eo0 eo1 ic p50 p51 regosc x1 x2 gnd regcpu p06 p05 p04/intp4 p03/intp3 p02/intp2 p01/intp1 p00/intp0 p125 p124 p123 p122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
7 m pd178023, 178024 data sheet u14126ej1v0ds00 ? 80-pin plastic qfp (14 14 mm, 0.65 pitch) m pd178023gc- -8bt, 178024gc- -8bt cautions 1. directly connect the ic (internally connected) to gnd. 2. keep the voltage at v dd port and v dd pll at the same voltage as v dd . 3. keep the voltage at gndport and gndpll at the same voltage as gnd. 4. connect each of the regosc and regcpu pins to gnd via 0.1- m f capacitor. p37 p36/beep0 p35 p34/ti51 p33/ti50 p32 p31 p30 p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 p55 p54 p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p70/si3 p71/so3 p72/sck3 p73 p74/rxd0 p75/txd0 p76/sda0 p77/scl0 p130/to50 p131/to51 p132 p40 p41 p42 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset v dd regosc x1 x2 gnd regcpu p06 p05 p04/intp4 p03/intp3 p02/intp2 p01/intp1 p00/intp0 p125 p124 p123 p122 p121 p120 gndport v dd port p43 p44 p45 p46 p47 amifc fmifc v dd pll vcoh vcol gndpll eo0 eo1 ic p50 p51 p52 p53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
8 m pd178023, 178024 data sheet u14126ej1v0ds00 pin name amifc : am intermediate frequency counter input ani0-ani5 : a/d converter input beep0 : buzzer output eo0, eo1 : error out output fmifc : fm intermediate frequency counter input gnd : ground gndpll : pll ground gndport : port ground ic : internally connected intp0-intp4 : interrupt input p00-p06 : port 0 p10-p15 : port 1 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5 p60-p67 : port 6 p70-p77 : port 7 p120-p125 : port 12 p130-p132 : port 13 regcpu : regulator for cpu power supply regosc : regulator for oscillator reset : reset input rxd0 : serial (uart0) data input sck3 : serial (sio3) clock input/output scl0 : serial (iic0) clock input/output sda0 : serial (iic0) data input/output si3 : serial (sio3) data input so3 : serial (sio3) data output ti50, ti51 : 8-bit timer clock input to50, to51 : 8-bit timer output txd0 : serial (uart0) data output vcol, vcoh: local oscillation input v dd : power supply v dd pll : pll power supply v dd port : port power supply x1, x2 : crystal resonator
9 m pd178023, 178024 data sheet u14126ej1v0ds00 block diagram remark the internal rom and ram capacities differ depending on the product. 78k/0 cpu core rom ram 8-bit timer/ event counter50 8-bit timer/ event counter51 watchdog timer basic timer serial interface3 i 2 c bus interrupt control uart0 buzzer output system control voltage regulator reset cpu peripheral v osc v cpu reset x1 x2 v dd port gndport v dd regosc regcpu gnd ti50/p33 to50/p130 ti51/p34 to51/p131 si3/p70 so3/p71 sck3/p72 sda0/p76 scl0/p77 intp0/p00- intp4/p04 5 (rxd0)/p74 (txd0)/p75 beep0/p36 port0 p00-p06 port1 port3 port4 port5 port6 port7 port12 port13 a/d converter frequency counter pll pll voltage regulator 7 6 8 8 8 8 8 6 3 6 p10-p15 p30-p37 p40-p47 p50-p57 p60-p67 p70-p77 p120-p125 p130-p132 ani0/p10- ani5/p15 amifc fmifc eo0 eo1 vcol vcoh v dd pll gndpll ic
10 m pd178023, 178024 data sheet u14126ej1v0ds00 contents 1. pin function list ...................................................................................................................... 11 1.1 port pins ............................................................................................................................... .. 11 1.2 pins other than port pins ................................................................................................... 12 1.3 i/o circuits of pins and recommended connections of unused pins ......................... 13 2. memory space ............................................................................................................................ 16 2.1 memory size select register (ims) .................................................................................... 17 2.2 internal extension ram size select register (ixs) ......................................................... 18 3. features of peripheral hardware functions .......................................................... 19 3.1 ports ............................................................................................................................... ......... 19 3.2 clock generation circuit ..................................................................................................... 20 3.3 timers ............................................................................................................................... ...... 20 3.4 buzzer output control circuit ............................................................................................. 22 3.5 a/d converter ........................................................................................................................ 23 3.6 serial interface ...................................................................................................................... 24 3.7 pll frequency synthesizer ................................................................................................ 26 3.8 frequency counter ............................................................................................................... 27 4. interrupt function ................................................................................................................. 28 5. standby function .................................................................................................................... 31 6. reset function ......................................................................................................................... 31 7. instruction set ........................................................................................................................ 32 8. electrical specifications ................................................................................................... 35 9. package drawing ..................................................................................................................... 44 10. recommended soldering conditions ............................................................................. 46 appendix a. development tools ............................................................................................. 47 appendix b. related documents ............................................................................................ 49
11 m pd178023, 178024 data sheet u14126ej1v0ds00 1. pin function list 1.1 port pins pin name i/o function at reset shared by: p00-p04 i/o port 0. input intp0-intp4 7-bit i/o port. p05, p06 can be set in input or output mode in 1-bit units. p10-p15 input port 1. input ani0-ani5 6-bit input port. p30-p32 i/o port 3. input p33 8-bit i/o port. ti50 p34 can be set in input or output mode in 1-bit units. ti51 p35 p36 beep0 p37 p40-47 i/o port 4. input 8-bit i/o port. can be set in input or output mode in 1-bit units. internal pull-up resistors can be specified in software. interrupt function by key input is provided. p50-p57 i/o port 5. input 8-bit i/o port. can be set in input or output mode in 1-bit units. p60-p67 i/o port 6. input 8-bit i/o port. can be set in input or output mode in 1-bit units. p70 i/o port 7. input si3 p71 8-bit i/o port. so3 p72 can be set in input or output mode in 1-bit units. sck3 p73 p74 rxd0 p75 txd0 p76 sda0 p77 scl0 p120-p125 i/o port 12. input 6-bit i/o port. can be set in input or output mode in 1-bit units. p130 output port 13. low-level to50 p131 3-bit output port. output to51 p132 n-ch open-drain output port (12 v withstand)
12 m pd178023, 178024 data sheet u14126ej1v0ds00 1.2 pins other than port pins pin name i/o function at reset shared by: intp0-intp4 input external maskable interrupt input whose valid edge input p00-p04 (rising edge, falling edge, or both rising and falling edges) can be specified. si3 input serial data input to serial interface. input p70 so3 output serial data output from serial interface. input p71 sda0 i/o serial data input/output to/from n-ch open drain i/o input p76 serial interface. sck3 i/o serial clock input/output to/from serial interface. input p72 scl0 n-ch open drain i/o p77 rxd0 input serial data input to asynchronous serial interface (uart0). input p74 txd0 output serial data output from asynchronous serial interface (uart0). p75 ti50 input external count clock input to 8-bit timer (tm50). input p33 ti51 external count clock input to 8-bit timer (tm51). p34 to50 output 8-bit timer (tm50) output. low-level p130 to51 8-bit timer (tm51) output. output p131 beep0 output buzzer output. input p36 ani0-ani5 input analog input to a/d converter. input p10-p15 eo0, eo1 output error out output from charge pump of pll frequency C C synthesizer. vcol input inputs local oscillation frequency of pll (in hf and mf modes). C C vcoh inputs local oscillation frequency of pll (in vhf mode). amifc input input to am intermediate frequency counter. input C fmifc input to fm or am intermediate frequency counter. reset input system reset input. C C x1 input connection of crystal resonator for system clock oscillation. C C x2 C CC regosc C regulator for oscillator. connect this pin to gnd via 0.1- m fC C capacitor. regcpu C regulator for cpu power supply. connect this pin to gnd C C via 0.1- m f capacitor. v dd C positive power supply. C C gnd C ground. C C v dd port C port power supply. C C gndport C port ground. C C v dd pll note C pll positive power supply. C C gndpll note C pll ground. C C ic C internally connected. directly connect this pin to gnd. C C note connect a capacitor of about 1000 pf between the v dd pll and gndpll pins.
13 m pd178023, 178024 data sheet u14126ej1v0ds00 1.3 i/o circuits of pins and recommended connections of unused pins table 1-1 shows the types of the i/o circuits of the respective pins and the recommended connections of the pins when they are not used. for the configuration of the i/o circuit of each pin, refer to figure 1-1. table 1-1. i/o circuit type of each pin pin name i/o circuit type i/o recommended connection of unused pin p00/intp0-p04/intp4 8 i/o set these pins in general-purpose input mode in software, and connect p05, p06 each of them to v dd , v dd port, gnd, or gndport via resistor. p10/ani0-p15/ani5 25 input connect each of them to v dd , v dd port, gnd, or gndport via resistor. p30-p32 5 i/o set these pins in general-purpose input mode in software, and output p33/ti50 5-k low-level signal. leave unconnected. p34/ti51 p35 5 p36/beep0 p37 p40-p47 5-a set these pins in general-purpose input mode in software, and connect each of them to gnd or gndport via resistor. p50-p57 5 set these pins in general-purpose input mode in software, and connect each of them to v dd , v dd port, gnd, or gndport via resistor. p60-p67 5 set these pins in general-purpose input mode in software, and output low-level signal. leave unconnected. p70/si3 5-k set these pins in general-purpose input mode in software, and connect each p71/so3 5 of them to v dd , v dd port, gnd, or gndport via resistor. p72/sck3 5-k p73 5 p74/rxd0 5-k p75/txd0 5 p76/sda0 10-d p77/scl0 p120-p125 5 p130/to50 19 output set these pins to low-level output in software and leave unconnected. p131/to51 p132 eo0, eo1 dts-eo1 output leave unconnected. vcol, vcoh dts-amp input disable pll in software and select pull-down. amifc, fmifc set these pins in general-purpose input port mode in software and connect each of them to v dd , v dd port, gnd, or gndport via resistor. regosc, regcpu C C connect these pins to gnd via 0.1- m f capacitor. reset 2 input C v dd pll C C connect this pin to v dd . gndpll directly connect these pins to gnd or gndport. ic
14 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 1-1. i/o circuits of respective pins (1/2) remark v dd and gnd are the positive power supply and ground pins for all port pins. take v dd and gnd as v dd port and gndport. type 2 type 5 type 5-a type 5-k type 8 type 10-d in schmitt trigger input with hysteresis characteristics v dd p-ch p-ch n-ch in/out pullup enable data output disable input enable v dd p-ch n-ch in/out data output disable v dd p-ch n-ch in/out data output disable input enable v dd p-ch n-ch in/out data output disable input enable v dd data output disable p-ch in/out v dd n-ch input enable open drain
15 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 1-1. i/o circuits of respective pins (2/2) note this switch is selectable in software only for the vcol and vcoh pins. remark v dd and gnd are the positive power supply and ground pins for all port pins. take v dd and gnd as v dd port and gndport. type 25 input enable comparator + n-ch p-ch v ref (threshold voltage) in type dts-amp type dts-eo1 v dd pll gndpll dw up p-ch out v dd pll gndpll n-ch note type 19 out n-ch in
16 m pd178023, 178024 data sheet u14126ej1v0ds00 2. memory space figure 2-1 shows the memory map of the m pd178023, 178024. figure 2-1. memory map note the internal rom and internal high-speed ram capacities differ depending on the model (refer to the table below). target model name internal rom end address internal high-speed ram first address nnnnh mmmmh m pd178023 5fffh fb00h m pd178024 7fffh fb00h ffffh ff0 0h feffh fee0h fedfh mmmmh nnnnh 0000h 0000h 003fh 0040h 007fh 0080h 07ffh 0800h 0fffh 1000h nnnnh mm mm h - 1 nn nn h + 1 cannot be used data memory space program memory space vector table area callf entry area program area callt table area program area special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note internal rom note
17 m pd178023, 178024 data sheet u14126ej1v0ds00 2.1 memory size select register (ims) the memory size select register (ims) sets the internal memory capacity. set the m pd178023, m pd178024 to c6h, c8h respectively. use an 8-bit memory manipulation instruction to set the ims. this register is set to cfh at reset. caution be sure to set the ims to c6h or c8h as the program initial setting. the ims set value changes to cfh when reset. therefore, set c6h or c8h again after reset. figure 2-2. format of memory size select register (ims) ram2 ram1 ram0 selects internal high-speed ram capacity 1 1 0 1024 bytes others setting prohibited ram3 ram2 ram1 ram0 selects internal rom capacity 0110 24k bytes 1000 32k bytes others setting prohibited table 2-1 indicates the setting of ims. table 2-1. set value of memory size select register (ims) targeted model set value of ims m pd178023 c6h m pd178024 c8h 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims at reset cfh r/w r/w address fff0h
18 m pd178023, 178024 data sheet u14126ej1v0ds00 2.2 internal extension ram size select register (ixs) the internal extension ram size select register (ixs) sets the internal extension ram capacity. use the m pd178023, m pd178024 with the initial value (0ch). use an 8-bit memory manipulation instruction to set the ixs. this register is set to 0ch at reset. caution do not assign a value other than that the value at reset. figure 2-3. format of internal extension ram size select register (ixs) ixram4 ixram3 ixram2 ixram1 ixram0 selects internal extension ram capacity 011000 byte others setting prohibited table 2-2 indicates the setting of ixs. table 2-2. set value of internal extension ram size select register targeted model set value of ixs m pd178023, 178024 0ch 7 0 6 0 5 0 4 ixram4 3 i xram3 2 i xram2 1 i xram1 0 i xram0 symbol ixs at reset 0ch r/w r/w address fff4h
19 m pd178023, 178024 data sheet u14126ej1v0ds00 3. features of peripheral hardware functions 3.1 ports the following three types of ports are available: ? cmos input (port 1) : 6 pins ? cmos i/o (ports 0, 3 - 7, and 12) : 53 pins ? n-ch open-drain output (port 13) : 3 pins total : 62 pins table 3-1. port functions name pin name function port 0 p00-p06 i/o port. can be set in input or output mode in 1-bit units. port 1 p10-p15 input-only port port 3 p30-p37 i/o port. can be set in input or output mode in 1-bit units. port 4 p40-p47 i/o port. can be set in input or output mode in 1-bit units. port 5 p50-p57 i/o port. can be set in input or output mode in 1-bit units. port 6 p60-p67 i/o port. can be set in input or output mode in 1-bit units. port 7 p70-p77 i/o port. can be set in input or output mode in 1-bit units. port 12 p120-p125 i/o port. can be set in input or output mode in 1-bit units. port 13 p130-p132 n-ch open-drain output port
20 m pd178023, 178024 data sheet u14126ej1v0ds00 3.2 clock generation circuit the instruction execution time can be changed as follows: ? 0.45 m s/0.89 m s/1.78 m s/3.56 m s/7.11 m s (system clock: 4.5-mhz crystal resonator) note figure 3-1. block diagram of clock generation circuit 3.3 timers four timer channels are provided. ? basic timer : 1 channel ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel figure 3-2. block diagram of basic timer system clock oscillator x2 x1 stop 00 00 pcc2 pcc1 internal bus standby control circuit 2 f x 2 2 f x 2 3 f x 2 4 f x prescaler clock to other than peripheral hardware prescaler f x cpu clock (f cpu ) wait control circuit processor clock control register (pcc) pcc0 3 selector 0 divider circuit 4.5 mhz intbtm0
21 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 3-3. block diagram of 8-bit timer/event counter 50 figure 3-4. block diagram of 8-bit timer/event counter 51 internal bus 8-bit compare register 50 (cr50) 8-bit counter 50 (tm50) ti50/p33 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 3 coincidence ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/p130 f x /2 output latch (p130) selector selector mask circuit internal bus 8-bit compare register 51 (cr51) 8-bit counter 51 (tm51) ti51/p34 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 coincidence ovf clear 3 tcl512 tcl511 tcl510 internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion s r q r inv selector selector selector selector inttm51 to51/p131 s f x /2 11 output latch (p131) mask circuit timer clock select register 51 (tcl51) timer mode control register 51 (tmc51)
22 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 3-5. block diagram of watchdog timer osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 clock input control circuit divided clock select circuit run divider circuit f x /2 8 intwdt reset wdt mode signal 3 watchdog timer clock select register (wdcs) oscillation stabilization time select register (osts) watchdog timer mode register (wdtm) output control circuit division mode select circuit internal bus internal bus beep cl02 beep cl01 beep cl00 beep0 clock select register (beepcl0) beep0/p36 1 khz 1.5 khz 3 khz 4 khz output latch (p36) pm36 selector 3.4 buzzer output control circuit the buzzer output frequency is selected as follows. ? beep0 ... 1 khz/1.5 khz/3 khz/4 khz figure 3-6. block diagram of buzzer output control circuit (beep0)
23 m pd178023, 178024 data sheet u14126ej1v0ds00 3.5 a/d converter an a/d converter with a resolution of 8 bits 6 channels is provided. figure 3-7. block diagram of a/d converter ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 sample & hold circuit voltage comparator voltage comparator successive approximation register (sar) a/d conversion result register 3 (adcr3) control circuit control circuit v dd gnd adcs3 intad3 pfen3 adcs3 ads33 ads32 ads31 ads30 0 fr32 fr31 fr30 0 0 0 pfcm3 pfhrm3 power-fail comparison mode register 3 (pfm3) a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) 4 internal bus selector tap selector power-fail comparison threshold value register 3 (pft3)
24 m pd178023, 178024 data sheet u14126ej1v0ds00 3.6 serial interface the m pd178023 and 178024 have three serial interface channels. ? serial interface (iic0) ? serial interface (sio3) ? serial interface (uart0) figure 3-8. block diagram of serial interface (iic0) internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise elimination circuit noise elimination circuit coincidence signal iic shift register 0 (iic0) so0 latch iice0 d set clear q cl01, cl00 sda0/p76 scl0/p77 n-ch open- drain output data hold time correction circuit ack detection circuit wake up control circuit ack detection circuit stop condition detection circuit serial clock counter interrupt request signal generator serial clock control circuit serial clock wait control circuit prescaler intiic0 f x cld0 iic transfer clock select register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detection circuit dad0 smc0 dfc0 cl01 cl00
25 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 3-9. block diagram of serial interface (sio3) figure 3-10. block diagram of serial interface (uart0) internal bus 8 interrupt request signal generation circuit selector serial clock counter serial clock control circuit serial i/o shift registe 3 (sio3) si3/p70 so3/p71 p71 output latch pm71 pm72 sck3/p72 intcsi3 f x /2 4 f x /2 5 f x /2 6 p72 output latch internal bus receive buffer register 0 (rxb0) rxd0/p74 txd0/p75 p75 output latch pm75 receive shift register 0 (rx0) pe0 fe0 ove0 reception control circuit (parity check) transmit shift register 0 (txs0) transmission control circuit (parity append) intser0 intst0 baud rate generator f x /2-f x /2 8 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 intsr0 asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0)
26 m pd178023, 178024 data sheet u14126ej1v0ds00 3.7 pll frequency synthesizer figure 3-11. block diagram of pll frequency synthesizer internal bus internal bus pll mode select register (pllmd) pll data transfer register (pllns) pll ns0 pll md0 pll md1 pll rf2 pll rf1 pll rf0 pll ul0 pll reference mode register (pllrf) pll unlock f/f judge register (pllul) pll rf3 2 input select block programmable divider phase comparator ( -det) unlock f/f reference frequency generator 4.5 mhz 4 charge pump eo1 eo0 vcoh vcol mixer 2 f n f r pll data register (pllrl, pllrh, pllr0) f voltage control generator lowpass filter note note vcol dmd vcoh dmd note external circuit.
27 m pd178023, 178024 data sheet u14126ej1v0ds00 3.8 frequency counter figure 3-12. block diagram of frequency counter internal bus ifc md0 ifc ck1 ifc ck0 ifc jg0 if counter mode select register (ifcmd) if counter gate judge register (ifcjg) if counter control register (ifccr) ifc md1 ifc res ifc st input select block start/stop control block gate time control block if counter register (ifc) block 2 2 fmifc amifc
28 m pd178023, 178024 data sheet u14126ej1v0ds00 4. interrupt function the m pd178023 and 178024 have the following three types and 17 sources of interrupts: ? non-maskable : 1 note ? maskable : 16 note ? software : 1 note two types of watchdog interrupt sources (intwdt), non-maskable and maskable, are available, and either of them can be selected. table 4-1. interrupt sources default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 non-maskable C intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intky detection of key input of port 4 internal 0010h (b) 7 intiic0 end of transfer by serial interface iic0 0012h 8 intbtm0 generation of basic timer match signal 0014h 9 intad3 end of conversion by a/d converter 0016h 10CCC 0018h note 3 C 11 intcsi3 end of transfer by serial interface sio3 internal 001ah (b) 12 inttm50 generation of coincidence signal of 8-bit 001ch timer/event counter 50 13 inttm51 generation of coincidence signal of 8-bit 001eh timer/event counter 51 14 intser0 reception error of serial interface uart0 0020h 15 intsr0 end of reception by serial interface uart0 0022h 16 intst0 end of transmission by serial interface uart0 0024h software C brk execution of brk instruction C 003eh (d) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. the default priority 0 is the highest, while 16 is the lowest. 2. (a) to (d) under the heading basic configuration type corresponds to (a) to (d) in figure 4-1. 3. there are no interrupt sources corresponding to vector addresses 0018h.
29 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 4-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt interrupt request priority control circuit vector table address generation circuit standby release signal internal bus interrupt request if mk ie pr isp standby release signal priority control circuit vector table address generation circuit internal bus if mk ie pr isp external interrupt rising/ falling edge enable registers (egp, egn) interrupt request standby release signal priority control circuit vector table address generation circuit internal bus edge detection circuit
30 m pd178023, 178024 data sheet u14126ej1v0ds00 figure 4-1. basic configuration of interrupt function (2/2) (d) software interrupt remark if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag interrupt request priority control circuit vector table address generation circuit internal bus
31 m pd178023, 178024 data sheet u14126ej1v0ds00 5. standby function there are the following two standby functions to reduce the system power consumption. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the system clock oscillation is stopped. all operations by the system clock are stopped and current consumption can be considerably reduced. figure 5-1. standby function 6. reset function there are the following three reset methods. ? external reset input by reset pin ? internal reset by watchdog timer runaway time detection ? internal reset by power-on clear (poc). system clock operation stop mode (system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation continued) interrupt request interrupt request halt instruction stop instruction
32 m pd178023, 178024 data sheet u14126ej1v0ds00 7. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc mov mov add addc sub subc and or xor cmp inc dec b,c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 rol4 [hl] mov [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
33 m pd178023, 178024 data sheet u14126ej1v0ds00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw xchw rp note sfrp movw saddrp movw !addr16 movw sp movw none incw decw push pop
34 m pd178023, 178024 data sheet u14126ej1v0ds00 (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr set1 clr1 set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
35 m pd178023, 178024 data sheet u14126ej1v0ds00 8. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd C0.3 to +6.0 v v dd port C0.3 to v dd + 0.3 v v dd pll C0.3 to v dd + 0.3 v input voltage v i C0.3 to +11.0 v output voltage v o excluding p130 to p132 C0.3 to v dd + 0.3 v output breakdown v bds p130-p132 n-ch open drain 16 v voltage analog input voltage v an p10-p15 analog input pin C0.3 to v dd + 0.3 v high-level output i oh 1 pin C8 ma current total of p00-p06, p30-p37, p54-p57, p60-p67, C15 ma and p120-p125 total of p40-p47, p50-p53, and p70-p77 C15 ma low-level output i ol note 1 pin peak value 16 ma current r.m.s 8 ma total of p00-p06, p30-p37, p40-p47, peak value 30 ma p50-p57, p60-p67, p70-p77, r.m.s 15 ma p120-p125, and p130-p132 operating temperature t a C40 to +85 c storage temperature t stg C55 to +125 c note calculate the r.m.s as follows: [r.m.s] = [peak value] x ? duty caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. be sure to use the product with these ratings never being exceeded. remark unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. recommended supply voltage ranges (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu is operating and pll is stopped 3.5 5.0 5.5 v data retention voltage v ddr when crystal oscillation stops 2.3 5.5 v output breakdown v bds p130-p132 (n-ch open drain) 15 v voltage
36 m pd178023, 178024 data sheet u14126ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (1/2) parameter symbol test conditions min. typ. max. unit high-level input v ih1 p10-p15, p30-p32, p35-p37, p40-p47, p50-p57, 0.7 v dd v dd v voltage p60-p67, p71, p73, p120-p125 v ih2 p00-p06, p33, p34, p70, p72, p74-p75, reset 0.8 v dd v dd v v ih3 p76, p77 4.5 v v dd 5.5 v 0.7 v dd v dd v (n-ch open-drain i/o) low-level input v il1 p10-p15, p30-p32, p35-p37, p40-p47, p50-p57, 0 0.3 v dd v voltage p60-p67, p71, p73, p120-p125 v il2 p00-p06, p33, p34, p70, p72, p74-p75, reset 0 0.2 v dd v v il3 p76, p77 4.5 v v dd 5.5 v 0 0.3 v dd v (n-ch open-drain i/o) high-level output v oh1 p00-p06, p30-p37, 4.5 v v dd 5.5 v, v dd C 1.0 v voltage p40-p47, p50-p57, i oh = C1 ma p60-p67, p70-p77, 3.5 v v dd < 4.5 v, v dd C 0.5 v p120-p125 i oh = C100 m a v oh2 eo0, eo1 v dd = 4.5 to 5.5 v, v dd C 1.0 v i oh = C3 ma low-level output v ol1 p00-p06, p30-p37, 4.5 v v dd 5.5 v, 1.0 v voltage p40-47, p50-57, p60-p67, i ol = 1 ma p70-p75, p120-p125 3.5 v v dd < 4.5 v, 0.5 v i ol = 100 m a v ol2 eo0, eo1 v dd = 4.5 to 5.5 v, 1.0 i ol = 3 ma v ol3 p76, p77 4.5 v v dd 5.5 v 0.4 v (n-ch open-drain i/o) i ol = 3 ma 4.5 v v dd 5.5 v 0.6 v i ol = 6 ma high-level input i lh p00-p06, p10-p15, v in = v dd 3 m a leakage current p30-p37, p40-p47, p50-p57, p60-p67, p70-p77, p120-p125, reset remark unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
37 m pd178023, 178024 data sheet u14126ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (2/2) parameter symbol test conditions min. typ. max. unit low-level input i lil p00-p06, p10-p15, v in = 0 v C3 m a leakage current p30-p37, p40-p47, p50-p57, p60-p67, p70-p77, p120-p125, reset output off i loh1 p130-p132 v out = 15 v C3 m a leakage current i lol1 p130-p132 v out = 0 v 3 m a i loh2 p76, p77 v out = v dd C3 m a (at n-ch open drain i/o) i lol2 p76, p77 v out = 0 v 3 m a (at n-ch open drain i/o) i loh3 eo0, eo1 v out = v dd C3 m a i lol3 eo0, eo1 v out = 0 v 3 m a supply current note i dd1 when cpu is operating and pll is stopped. 4.0 20 ma sine wave input to x1 pin at f x = 4.5 mhz v in = v dd i dd2 in halt mode with pll stopped. 0.35 0.70 ma sine wave input to x1 pin at f x = 4.5 mhz v in = v dd data retention v ddr1 when crystal resonator is oscillating 3.5 5.5 v voltage v ddr2 when crystal oscillation is power-failure detection 2.2 v stopped function v ddr3 data memory retained 2.0 v data retention i ddr1 when crystal oscillation is t a = 25 c, 2.0 4.0 m a current stopped v dd = 5 v i ddr2 2.0 20 m a note excluding av dd current and v dd pll current. remarks 1. f x : system clock oscillation frequency 2. unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
38 m pd178023, 178024 data sheet u14126ej1v0ds00 reference characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current i dd3 when cpu and pll are operating. 8 ma sine wave input to vcoh pin at f in = 160 mhz v in = 0.15 v p-p ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy f x = 4.5 mhz 0.44 7.11 m s (minimum instruction execution time) ti50, ti51 input f ti5 2 mhz frequency ti50, ti51 input t tih5 200 ns high-/low-level widths t til5 interrupt input t inth intp0-intp4 1 m s high-/low-level widths t intl reset pin t rsl 10 m s low-level width
39 m pd178023, 178024 data sheet u14126ej1v0ds00 (2) serial interface (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface (iic0) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus free time (between stop and start t buf 4.7 C 1.3 C m s conditions) hold time note 1 t hd : sta 4.0 C 0.6 C m s scl0 clock low-level width t low 4.7 C 1.3 C m s scl0 clock high-level width t high 4.0 C 0.6 C m s start/restart condition setup time t su : sta 4.7 C 0.6 C m s data hold cbus compatible master t hd : dat 5.0 C C C m s time i 2 c bus 0 note 2 C0 note 2 0.9 note 3 m s data setup time t su : dat 250 C 100 note 4 Cns sda0 and scl0 signal rise time t r C 1000 20+0.1cb note 5 300 ns sda0 and scl0 signal fall time t f C 300 20+0.1cb note 5 300 ns stop condition setup time t su : sto 4.0 C 0.6 C m s pulse width of spike restrained by input filter t sp C C 0 50 ns each bus line capacitative load cb C 400 C 400 pf notes 1. the first clock pulse is generated at the start condition after this period. 2. the device needs to internally supply a hold time of at least 300 ns for the sda0 signal to fill the undefined area at the falling edge of the scl0 (v ihmin. of the scl0 signal). 3. unless the device extends the low hold time (t low ) of the scl0 signal, it is necessary to fill only the maximum data hold time (t hd : dat ). 4. the high-speed mode i 2 c bus can be used in the standard mode i 2 c bus system. in this case, satisfy the following conditions: ? when the device does not extend the low hold time of the scl0 signal t su : dat 3 250 ns ? when the device extends the low hold time of the scl0 signal send the next data bit to the sda line before releasing the scl0 line (t rmax. + t su:dat = 1000 + 250 = 1250 ns : in the standard mode i 2 c bus specification) 5. cb: total capacitance of one bus line (unit: pf)
40 m pd178023, 178024 data sheet u14126ej1v0ds00 (b) serial interface (sio3) (i) 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck3 cycle time t kcy1 800 ns sck3 high/low-level width t kh1 ,t kcy1 /2 C 50 ns t kl1 si3 setup time (to sck3 - )t sik1 100 ns si3 hold time (from sck3 - )t ksi1 400 ns sck3 ? so3 output delay time t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck3 and so3 output line. (ii) 3-wire serial i/o mode (sck3 ... external clock input) parameter symbol test conditions min. typ. max. unit sck3 cycle time t kcy2 800 ns sck3 high/low-level width t kh2 , 400 ns t kl2 si3 setup time (to sck3 - )t sik2 100 ns si3 hold time (from sck3 - )t ksi2 400 ns sck3 ? so3 output delay time t kso2 c = 100 pf note 300 ns sck3 at rising or falling edge time t r2 , t f2 1000 ns note c is the load capacitance of so3 output line. (d) serial interface (uart0: dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate 38400 bps
41 m pd178023, 178024 data sheet u14126ej1v0ds00 ac timing test point (excluding x1 input) ti timing interrupt input timing reset input timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 1/f ti5 t til5 t tih5 ti50,ti51 t intl t inth intp0 to intp4 t rsl reset
42 m pd178023, 178024 data sheet u14126ej1v0ds00 serial transfer timing i 2 c bus mode: 3-wire serial i/o mode: remark m = 1, 2 n = 2 t kcym t klm t khm sck3 si3 so3 t sikm t ksim t ksom input data output data t rn t fn t low t r t hd : dat t f t high t hd : sta t su : sta t hd : sta t sp t su : sto t buf scl0 sda0 t su : dat stop condition start condition restart condition stop condition
43 m pd178023, 178024 data sheet u14126ej1v0ds00 a/d converter characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit resolution 888bit total conversion 0.8 % error note conversion time t conv 15.2 45.7 m s analog input voltage v ian 0v dd v note excluding quantization error ( 1/2lsb) pll characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating frequency f in1 vcol pin, mf mode, sine wave input, v in = 0.15 v p-p 0.5 3.0 mhz f in2 vcol pin, hf mode, sine wave input, v in = 0.15 v p-p 10 40 mhz f in3 vcoh pin, vhf mode, sine wave input, v in = 0.15 v p-p 60 130 mhz f in4 vcoh pin, vhf mode, sine wave input, v in = 0.3 v p-p 40 160 mhz ifc characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit operating frequency f in5 amifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p f in6 fmifc pin, fmif count mode, sine wave input, 10 11 mhz v in = 0.15 v p-p f in7 fmifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p
44 m pd178023, 178024 data sheet u14126ej1v0ds00 9. package drawing 80-pin plastic qfp (14x20) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.8 (t.p.) 0.8 j 17.6 0.4 k p80gf-80-3b9-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. h 0.37 + 0.08 - 0.07 m 0.17 + 0.08 - 0.07 64 65 40 80 1 25 24 41 s s n j detail of lead end c d a b r k m l p i s q g f m h
45 m pd178023, 178024 data sheet u14126ej1v0ds00 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 - 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 - 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
46 m pd178023, 178024 data sheet u14126ej1v0ds00 10. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. table 10-1. soldering conditions for surface-mount type m pd178023gf-xxx-3b9: 80-pin plastic qfp (14 20 mm, 0.8-mm pitch) m pd178024gf-xxx-3b9: 80-pin plastic qfp (14 20 mm, 0.8-mm pitch) soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec max. (210 c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 sec max. (200 c min.), vp15-00-3 number of times: 3 max. wave soldering solder bath temperature: 260 c max., time: 10 sec max., ws60-00-1 number of times: 1, preheating temperature: 120 c max., (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec max (per device side) C caution do not use two or more soldering methods in combination (except partial heating). m pd178023gc-xxx-8bt: 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178024gc-xxx-8bt: 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec max. (210 c min.), ir35-00-2 number of times: 2 max. vps package peak temperature: 215 c, time: 40 sec max. (200 c min.), vp15-00-2 number of times: 2 max. wave soldering solder bath temperature: 260 c max., time: 10 sec max., ws60-00-1 number of times: 1, preheating temperature: 120 c max., (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec max (per device side) C caution do not use two or more soldering methods in combination (except partial heating).
47 m pd178023, 178024 data sheet u14126ej1v0ds00 appendix a. development tools the following development tools are available for development of systems using the m pd178023, 178024 subseries. (1) language processor software ra78k0 notes 1, 2, 3 assembler package common to 78k/0 series cc78k0 notes 1, 2, 3 c compiler package common to 78k/0 series df178124 notes 1, 2, 3 device file for m pd178024 subseries cc78k0-l notes 1, 2, 3 c compiler library source file common to 78k/0 series (2) flash memory writing tools fashpro iii (part number: dedicated flash writer fl-pr3 note 4 , pg-fl3) fa-80gf note 4 flash memory writing adapter fa-80gc-8bt note 4 (3) debugging tools ? when in-circuit emulator ie-78k0-ns is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa note 5 performance board for enhancing and expanding the ie-78k0-ns function ie-70000-98-if-c interface adapter necessary when a pc-9800 series (except notebook-type pc) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable necessary when a notebook-type pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when a ibm pc/at tm compatible machine is used (isa bus supported) ie-70000-pci-if interface adapter necessary when a pc with a pci bus is used as host machine ie-178134-ns-em1 note 5 emulation board for emulating the m pd178024 subseries np-80gf note 4 emulation probe for 80-pin plastic qfp (gf-3b9 type) ev-9200g-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gf-3b9 type) np-80gc note 4 emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gc-8bt type) sm78k0 notes 1, 2 system simulator common to 78k/0 series id78k0-ns notes 1, 2 integrated debugger common to 78k/0 series df178124 notes 1, 2, 3 device file for m pd178024 subseries notes 1. pc-9800 series (ms-dos tm + windows tm ) based 2. ibm pc/at compatible machine (japanese/english windows) based 3. hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm (sunos tm , solaris tm ) based, news tm (new-os tm ) based 4. products of naito densei machida mfg. co., ltd. (tel: 044-822-3813). consult nec distributor when purchasing these products. 5. under development remark use the ra78k0, cc78k0, and sm78k0 in combination with the df178124.
48 m pd178023, 178024 data sheet u14126ej1v0ds00 ? when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter necessary when a pc-9800 series (except notebook-type pc) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter when a ibm pc/at compatible machine is used (isa bus supported) ie-70000-pci-if interface adapter necessary when a pc with a pci bus is used as host machine ie-78000-r-sv3 interface adapter and cable necessary when an ews is used as host machine ie-178134-ns-em1 note4 emulation board for emulating the m pd178024 subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-178134-ns-em1 on ie-78001-r-a. ep-78130gf-r emulation probe for 80-pin plastic qfp (gf-3b9 type) ev-9200g-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gf-3b9 type) ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gc-8bt type) sm78k0 notes 1, 2 system simulator common to 78k/0 series id78k0 notes 1, 2 integrated debugger common to 78k/0 series df178124 notes 1, 2, 3 device file for m pd178024 subseries real-time os rx78k0 notes 1, 2, 3 real-time os for 78k/0 series mx78k0 notes 1, 2, 3 os for 78k/0 series notes 1. pc-9800 series (ms-dos + windows) based 2. ibm pc/at compatible machine (japanese/english windows) based 3. hp9000 series 700 (hp-ux) based, sparcstation (sunos, solaris) based, news (new-os) based 4. under development remark use sm78k0 in combination with the df178124.
49 m pd178023, 178024 data sheet u14126ej1v0ds00 appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device documents title document no. japanese english m pd178023, 178024 data sheet u14126j this document m pd178024, 178124 subseries users manual u13915j u13915e 78k/0 series users manualinstruction u12326j u12326e 78k/0 series instruction set u10904j 78k/0 series instruction table u10903j 78k/0 series application note basics (i) u12704j u12704e development tool documents (users manual) title document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly u11789j u11789e language ra78k series structured assembler preprocessor u12323j eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e ie-78001-r-a to be prepared to be prepared ie-78k0-ns u13731j to be prepared ie-178134-ns-em1 to be prepared to be prepared ep-78230 eeu-985 eeu-1515 ep-78130 C eeu-1470 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external parts user u10092j u10092e open interface specifications id78k0 integrated debugger ews based reference u11151j C id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e id78k0-ns integrated debugger windows based reference u12900j u12900e caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
50 m pd178023, 178024 data sheet u14126ej1v0ds00 related documents for embedded software (users manual) title document no. japanese english 78k/0 series real-time os fundamental u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 fundamental u12257j u12257e other documents title document no. japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality guides on nec semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality/reliability handbook c12769j microcomputer product series guide u11416j caution the contents of the above documents are subject to change without notice. ensure that the latest versions are used in design work, etc.
51 m pd178023, 178024 data sheet u14126ej1v0ds00 [memo]
52 m pd178023, 178024 data sheet u14126ej1v0ds00 [memo]
53 m pd178023, 178024 data sheet u14126ej1v0ds00 [memo]
54 m pd178023, 178024 data sheet u14126ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. iebus is a trademark of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
55 m pd178023, 178024 data sheet u14126ej1v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd178023, 178024 the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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